BIST Design Automation and Fault Emulation: BFE Tool
نویسنده
چکیده
1 This work has been partially funded by FCT (Portugal), POCTI/ESE41788/2001. Abstract. This paper describes a new tool for Built in Self Test (BIST) design automation and fault emulation (FE). Combinational and/or sequential digital modules may be designed with embedded self-test attributes. Linear Feedback Shift Registers (LFSRs) and Multiple Input Shift Registers (MISRs) are automatically generated and connected to the circuit under test (CUT), implementing different BIST possible architectures. The controller for the emulation process is also automatically generated. Hardware fault emulation (HFE) is especially rewarding for sequential modules, and for comparing different BIST architectures. The methodology is fully automated for Xilinx Spartan2 FPGAs. Results, using a Digilab2 board, ISCAS’85 and ITC99 benchmarks, show that fault emulation can be used for efficient selection of the BIST architecture and LFSR seed, with significant impact on BIST quality.
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